Cut and paste this URL to share the unmodified register and value:
https://regviz.com/r/Microchip Technology/ATSAMV71J20/SCB/CCSIDR#0x0
Cache Size ID Register
number of words in each cache line
number of ways
number of sets
Write allocation support
Read allocation support
Write-Back support
Write-Through support
https://github.com/cmsis-svd/cmsis-svd-data